M25P64
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in
is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
SPI Memory
Device
SPI Memory
Device
C Q D
C Q D
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
CPOL
CPHA
C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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