M24128-BW, M24128-BR, M24256-BW, M24256-BR
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits,
b15-b6, are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implemen-
tation dependent way.
The bus master sends from 1 to 64 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 6 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
BYTE WRITE
DEV SEL
ACK
ACK
DATA IN
ACK
BYTE ADDR
R/W
BYTE ADDR
START
WC
ACK
PAGE WRITE
DEV SEL
ACK
ACK
DATA IN 1
ACK
DATA IN 2
BYTE ADDR
R/W
BYTE ADDR
WC (cont'd)
START
ACK
PAGE WRITE
(cont'd)
DATA IN N
ACK
STOP
STOP
AI01106C
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STMICROELECTRONICS [ STMICROELECTRONICS ]
