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M24256-BWMN6TP 参数 Datasheet PDF下载

M24256-BWMN6TP图片预览
型号: M24256-BWMN6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 256Kbit和128Kbit的串行I2C总线的EEPROM采用三片选线 [256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines]
分类和应用: 存储内存集成电路光电二极管双倍数据速率PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 25 页 / 456 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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M24128-BW, M24128-BR, M24256-BW, M24256-BR
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
BYTE WRITE
DEV SEL
ACK
ACK
NO ACK
DATA IN
BYTE ADDR
R/W
BYTE ADDR
START
WC
ACK
PAGE WRITE
DEV SEL
ACK
ACK
NO ACK
DATA IN 1
DATA IN 2
BYTE ADDR
R/W
BYTE ADDR
WC (cont'd)
NO ACK
PAGE WRITE
(cont'd)
NO ACK
START
DATA IN N
STOP
STOP
AI01120C
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the R/W bit (RW) reset
to 0. The device acknowledges this, as shown in
and waits for two address bytes. The de-
vice responds to each address byte with an ac-
knowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not
acknowledged, as shown in
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
is sent first, followed by the Least Signifi-
cant Byte (Table
Bits b15 to b0 form the
address of the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay t
W
, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
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