LIS3DH
Mechanical and electrical specifications
2
2.4.2
I C - Inter IC control interface
Subject to general operating conditions for Vdd and top.
2
Table 7.
I C slave timing values
2
(1)
2
(1)
I C standard mode
I C fast mode
Min
Symbol
Parameter
Unit
kHz
µs
Min
0
Max
Max
f(SCL)
tw(SCLL)
tw(SCLH)
tsu(SDA)
SCL clock frequency
SCL clock low time
SCL clock high time
SDA setup time
100
0
400
4.7
4.0
250
0.01
1.3
0.6
100
0.01
ns
µs
th(SDA)
SDA data hold time
SDA and SCL rise time
3.45
1000
300
0.9
300
300
(2)
t
r(SDA) tr(SCL)
20 + 0.1Cb
ns
(2)
tf(SDA) f(SCL)
th(ST)
tsu(SR)
t
SDA and SCL fall time
20 + 0.1Cb
0.6
START condition hold time
4
4.7
4
Repeated START condition
setup time
0.6
0.6
1.3
µs
tsu(SP)
STOP condition setup time
Bus free time between STOP
and START condition
tw(SP:SR)
4.7
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
2
Figure 4. I C Slave timing diagram
REPEATED
START
START
t
su(SR)
START
t
w(SP:SR)
SDA
t
t
h(SDA)
su(SDA)
t
f(SDA)
t
r(SDA)
STOP
t
su(SP)
SCL
t
h(ST)
t
t
t
r(SCL)
t
f(SCL)
w(SCLL)
w(SCLH)
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both port.
Doc ID 17530 Rev 1
13/42
STMICROELECTRONICS [ ST ]
