Mechanical and electrical specifications
LIS3DH
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6.
SPI slave timing values
Value (1)
Symbol
Parameter
Unit
Min
Max
tc(SPC)
SPI clock cycle
100
ns
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
SPI clock frequency
CS setup time
10
MHz
6
8
CS hold time
SDI input setup time
SDI input hold time
5
15
ns
tv(SO)
th(SO)
tdis(SO)
SDO valid output time
SDO output hold time
SDO output disable time
50
50
9
Figure 3. SPI slave timing diagram
CS
(3)
(3)
(3)
(3)
(3)
tc(SPC)
tsu(CS)
th(CS)
SPC
SDI
tsu(SI)
th(SI)
LSB IN
MSB IN
(3)
tdis(SO)
tv(SO)
th(SO)
MSB OUT
LSB OUT
(3)
(3)
SDO
Note:
1
Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on
characterization results, not tested in production.
2
3
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port.
When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal
pull-up resistors.
12/42
Doc ID 17530 Rev 1
STMICROELECTRONICS [ ST ]
