FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
There are no IAP counterparts for the external host com-
mands Select-Block0 and Select-Block1.
4.2.6 Interrupt Termination
If interrupt termination is selected, (SFCM[7] is set), then
an interrupt (INT1) will be generated to indicate flash opera-
tion completion. Under this condition, the INT1 becomes an
internal interrupt source. The INT1# pin can now be used
as a general purpose port pin and it cannot be the source
of External Interrupt 1 during in-application programming.
4.2.5 Polling
A command that uses the polling method to detect flash
operation completion should poll on the FLASH_BUSY bit
(SFST[2]). When FLASH_BUSY de-asserts (logic 0), the
device is ready for the next operation.
In order to use an interrupt to signal flash operation termi-
nation. EX1 and EA bits of IE register must be set. The IT1
bit of TCON register must also be set for edge trigger
detection.
MOVC instruction may also be used for verification of the
Programming and Erase operation of the flash memory.
MOVC instruction will fail if it is directed at a flash block that
is still busy.
.
TABLE
4-3: IAP Commands1
Operation
Chip-Erase3
SFCM [6:0]2
SFDT [7:0]
55H
SFAH [7:0]
SFAL [7:0]
01H
X4
AH
AH6
AH
AH
X
X
Block-Erase5
Sector-Erase5
Byte-Program5
Byte-Verify (Read)5
Prog-SB19
Prog-SB29
Prog-SB39
Prog-SC09
Enable-Clock-Double9
0DH
55H
X
0BH
X
DI8
AL7
AL
AL
X
0EH
0CH
DO8
AAH
AAH
AAH
AAH
AAH
0FH
03H
X
X
05H
X
X
09H
5AH
55H
X
08H
X
T4-3.0 1273
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
SFCM[7] =1: Interrupt enable for flash operation completion
0: polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be VIL or VIH, but no other value.
5. Refer to Table 4-2 for address resolution
6. AH = Address high order byte
7. AL = Address low order byte
8. DI = Data Input, DO = Data Output, all other values are in hex.
9. Instruction must be located in Block 1 or external code memory.
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
38
SST [ SILICON STORAGE TECHNOLOGY, INC ]
