FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
4.0 FLASH MEMORY PROGRAMMING
The device internal flash memory can be programmed or
erased using In-Application Programming (IAP) mode
4.2.1 In-Application Programming Mode Clock
Source
During IAP mode, both the CPU core and the flash control-
ler unit are driven off the external clock. However, an inter-
nal oscillator will provide timing references for Program and
Erase operations. The internal oscillator is only turned on
when required, and is turned off as soon as the flash oper-
ation is completed.
4.1 Product Identification
The Read-ID command accesses the Signature Bytes that
identify the device and the manufacturer as SST. External
programmers primarily use these Signature Bytes in the
selection of programming algorithms.
4.2.2 Memory Bank Selection for In-Application
Programming Mode
TABLE
4-1: Product Identification
Address
30H
Data
With the addressing range limited to 16 bit, only 64 KByte
of program address space is “visible” at any one time. As
shown in Table 4-2, the bank selection (the configuration of
EA# and SFCF[1:0]), allows Block 1 memory to be overlaid
on the lowest 8 KByte of Block 0 memory, making Block 1
reachable. The same concept is employed to allow both
Block 0 and Block 1 flash to be accessible to IAP opera-
tions. Code from a block that is not visible may not be used
as a source to program another address. However, a block
that is not “visible” may be programmed by code from the
other block through mailbox registers.
Manufacturer’s ID
Device ID
BFH
SST89E516RD2/RD
SST89V516RD2/RD
31H
31H
93H
92H
T4-1.0 1273
4.2 In-Application Programming Mode
The device offers either 72 KByte of in-application pro-
grammable flash memory. During in-application program-
ming, the CPU of the microcontroller enters IAP mode. The
two blocks of flash memory allow the CPU to execute user
code from one block, while the other is being erased or
reprogrammed concurrently. The CPU may also fetch code
from an external memory while all internal flash is being
reprogrammed. The mailbox registers (SFST, SFCM,
SFAL, SFAH, SFDT and SFCF) located in the special func-
tion register (SFR), control and monitor the device’s erase
and program process.
The device allows IAP code in one block of memory to pro-
gram the other block of memory, but may not program any
location in the same block. If an IAP operation originates
physically from Block 0, the target of this operation is implic-
itly defined to be in Block 1. If the IAP operation originates
physically from Block 1, then the target address is implicitly
defined to be in Block 0. If the IAP operation originates from
external program space, then, the target will depend on the
address and the state of bank selection.
Table 4-3 outline the commands and their associated mail-
box register settings.
4.2.3 IAP Enable Bit
The IAP enable bit, SFCF[6], enables in-application pro-
gramming mode. Until this bit is set, all flash programming
IAP commands will be ignored.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
34
SST [ SILICON STORAGE TECHNOLOGY, INC ]
