8 Mbit Firmware Hub
SST49LF008A
Data Sheet
TABLE 3: FWH Read Cycle
Clock
Cycle
Field
Name
Field Contents
FWH[3:0]1
FWH[3:0]
Direction
Comments
1
START
1101
IN
FWH4 must be active (low) for the part to respond. Only the
last start field (before FWH4 transitions high) should be rec-
ognized. The START field contents indicate a FWH memory
Read cycle.
2
IDSEL
IMADDR
IMSIZE
TAR0
0000 to 1111
YYYY
IN
IN
IN
Indicates which FWH device should respond. If the to IDSEL (ID
select) field matches the value ID[3:0], then that particular device
will respond to the whole bus cycle.
3-9
10
11
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
0000 (1 byte)
1111
A field of this size indicates how many bytes will be or trans-
ferred during multi-byte operations. The SST49LF008A will
only support single-byte operation. IMSIZE=0000b
IN
In this clock cycle, the master (Intel ICH) has driven the bus
then float to all ‘1’s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
then Float
12
13
TAR1
1111 (float)
Float
then OUT
The SST49LF008A takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync data.”
RSYNC
0000 (READY)
OUT
During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant nibble of
the least-significant byte will be available during the next
clock cycle.
14
15
16
DATA
DATA
TAR0
YYYY
YYYY
1111
OUT
OUT
YYYY is the least-significant nibble of the least-significant
data byte.
YYYY is the most-significant nibble of the least-significant
data byte.
OUT
then Float
In this clock cycle, the SST49LF008A has driven the bus to
all ones and then floats the bus prior to the next clock cycle.
This is the first part of the bus “turnaround cycle.”
17
TAR1
1111 (float)
Float then
IN
The master (Intel ICH) resumes control of the bus during
this cycle.
T3.3 1161
1. Field contents are valid on the rising edge of the present clock cycle.
CLK
FWH4
STR
IDS
IMADDR
IMS
TAR
RSYNC
DATA
TAR
FWH[3:0]
1161 F09.0
FIGURE 6: Single-Byte Read Waveforms
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
