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SST39VF512-70-4C-WH 参数 Datasheet PDF下载

SST39VF512-70-4C-WH图片预览
型号: SST39VF512-70-4C-WH
PDF下载: 下载PDF文件 查看货源
内容描述: 512千位/ 1兆位/ 2兆位/ 4兆位( X8 )多用途闪存 [512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 24 页 / 283 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash  
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040  
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040  
Data Sheet  
pulse, while the command (30H) is latched on the rising  
edge of the sixth WE# pulse. The internal Erase operation  
begins after the sixth WE# pulse. The End-of-Erase can be  
determined using either Data# Polling or Toggle Bit meth-  
ods. See Figure 9 for timing waveforms. Any commands  
written during the Sector-Erase operation will be ignored.  
Device Operation  
Commands are used to initiate the memory operation func-  
tions of the device. Commands are written to the device  
using standard microprocessor write sequences. A com-  
mand is written by asserting WE# low while keeping CE#  
low. The address bus is latched on the falling edge of WE#  
or CE#, whichever occurs last. The data bus is latched on  
the rising edge of WE# or CE#, whichever occurs first.  
Chip-Erase Operation  
The SST39LF512/010/020/040 and SST39VF512/010/  
020/040 devices provide a Chip-Erase operation, which  
allows the user to erase the entire memory array to the 1s”  
state. This is useful when the entire device must be quickly  
erased.  
Read  
The Read operation of the SST39LF512/010/020/040 and  
SST39VF512/010/020/040 device is controlled by CE#  
and OE#, both have to be low for the system to obtain data  
from the outputs. CE# is used for device selection. When  
CE# is high, the chip is deselected and only standby power  
is consumed. OE# is the output control and is used to gate  
data from the output pins. The data bus is in high imped-  
ance state when either CE# or OE# is high. Refer to the  
Read cycle timing diagram for further details (Figure 4).  
The Chip-Erase operation is initiated by executing a six-  
byte Software Data Protection command sequence with  
Chip-Erase command (10H) with address 5555H in the last  
byte sequence. The internal Erase operation begins with  
the rising edge of the sixth WE# or CE#, whichever occurs  
first. During the internal Erase operation, the only valid read  
is Toggle Bit or Data# Polling. See Table 4 for the command  
sequence, Figure 10 for timing diagram, and Figure 18 for  
the flowchart. Any commands written during the Chip-  
Erase operation will be ignored.  
Byte-Program Operation  
The SST39LF512/010/020/040 and SST39VF512/010/  
020/040 are programmed on a byte-by-byte basis. Before  
programming, one must ensure that the sector, in which  
the byte which is being programmed exists, is fully erased.  
The Program operation consists of three steps. The first  
step is the three-byte-load sequence for Software Data  
Protection. The second step is to load byte address and  
byte data. During the Byte-Program operation, the  
addresses are latched on the falling edge of either CE# or  
WE#, whichever occurs last. The data is latched on the ris-  
ing edge of either CE# or WE#, whichever occurs first. The  
third step is the internal Program operation which is initi-  
ated after the rising edge of the fourth WE# or CE#, which-  
ever occurs first. The Program operation, once initiated, will  
be completed, within 20 µs. See Figures 5 and 6 for WE#  
and CE# controlled Program operation timing diagrams  
and Figure 15 for flowcharts. During the Program opera-  
tion, the only valid reads are Data# Polling and Toggle Bit.  
During the internal Program operation, the host is free to  
perform additional tasks. Any commands written during the  
internal Program operation will be ignored.  
Write Operation Status Detection  
The SST39LF512/010/020/040 and SST39VF512/010/  
020/040 devices provide two software means to detect the  
completion of a Write (Program or Erase) cycle, in order to  
optimize the system write cycle time. The software detec-  
tion includes two status bits: Data# Polling (DQ7) and Tog-  
gle Bit (DQ6). The End-of-Write detection mode is enabled  
after the rising edge of WE# which initiates the internal Pro-  
gram or Erase operation.  
The actual completion of the nonvolatile write is asynchro-  
nous with the system; therefore, either a Data# Polling or  
Toggle Bit read may be simultaneous with the completion  
of the Write cycle. If this occurs, the system may possibly  
get an erroneous result, i.e., valid data may appear to con-  
flict with either DQ7 or DQ6. In order to prevent spurious  
rejection, if an erroneous result occurs, the software routine  
should include a loop to read the accessed location an  
additional two (2) times. If both reads are valid, then the  
device has completed the Write cycle, otherwise the rejec-  
tion is valid.  
Sector-Erase Operation  
The Sector-Erase operation allows the system to erase the  
device on a sector-by-sector basis. The sector architecture  
is based on uniform sector size of 4 KByte. The Sector-  
Erase operation is initiated by executing a six-byte-com-  
mand sequence with Sector-Erase command (30H) and  
sector address (SA) in the last bus cycle. The sector  
address is latched on the falling edge of the sixth WE#  
©2001 Silicon Storage Technology, Inc.  
S71150-03-000 6/01 395  
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