512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
T
OE
OEH
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
A
A
= Most significant address
MS
MS
395 ILL F07.0
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
for SST39LF/VF020 and A for SST39LF/VF040
A
18
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555 5555 2AAA
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW0
SW5
334 ILL F08.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
SA = Sector Address
X
A
A
= Most significant address
MS
MS
= A for SST39LF/VF512, A for SST39LF/VF010, A for SST39LF/VF020 and A for SST39LF/VF040
15 16 17 18
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01 395
12
SST [ SILICON STORAGE TECHNOLOGY, INC ]
