1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
CP
CE#
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
1147 F05.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39SF010A, A for SST39SF020A, and A for SST39SF040
16 17 18
FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
OES
T
OEH
T
OE
DQ
7
D
D#
D#
D
1147 F06.1
Note:
A
A
= Most significant address
MS
MS
= A for SST39SF010A, A for SST39SF020A, and A for SST39SF040
16 17 18
FIGURE 7: DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71147-06-000
8/04
11
SST [ SILICON STORAGE TECHNOLOGY, INC ]
