2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
OE#
WE#
T
T
OES
T
OEH
OE
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
Note:
A
MS
A
MS
= Most significant address
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
16
17
18
1117 F07.3
FIGURE 9: Toggle Bit Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
SCE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
A
= Most significant address
MS
A
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
MS
16 17 18
X can be V or V , but no other value.
IL IH
1117 F08.7
FIGURE 10: WE# Controlled Chip-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71117-09-000
2/07
17
SST [ SILICON STORAGE TECHNOLOGY, INC ]
