2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
BE
5555
2AAA
5555
5555
2AAA
BA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX50
SW5
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
BA = Block Address
X
A
= Most significant address
MS
A
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
MS
16 17 18
X can be V or V , but no other value.
IL IH
1117 F17.9
FIGURE 11: WE# Controlled Block-Erase Timing Diagram
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
2AAA
5555
5555
2AAA
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
SA = Sector Address
X
A
= Most significant address
MS
A
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A
MS
16 17 18
X can be V or V , but no other value.
IL IH
1117 F18.8
FIGURE 12: WE# Controlled Sector-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71117-09-000
2/07
18
SST [ SILICON STORAGE TECHNOLOGY, INC ]
