512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
TOP VIEW (balls facing down)
6
5
4
3
2
1
A2
A1
A0
A8
A17 A14 A13
WE#
A9
A11 NC1 OE# A10 CE#
DQ7 DQ5 DQ6
DQ3 DQ4
DQ2
A0 DQ0 DQ1
V
DD
CE# A16 A18
V
SS
V
SS
A12 A15
A6
A7
A5
A4 NC2 A3
A2
A1
A B
C
D
E
F
G
H
J
Note: For SST39LF020, ball B3 is "No Connect"
For SST39LF010, balls B3 and A5 are "No Connect"
FIGURE 4: PIN ASSIGNMENT FOR 34-BALL WFBGA (4MM X 6MM) FOR 1 MBIT AND 2 MBIT
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
VSS
NC
Ground
No Connection
Unconnected pins.
T2.1 1150
1. AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
TABLE 3: OPERATION MODES SELECTION
Mode
Read
CE#
VIL
OE#
VIL
WE#
VIH
VIL
DQ
DOUT
DIN
X1
Address
AIN
Program
Erase
VIL
VIH
VIH
AIN
VIL
VIL
Sector address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 4
T3.4 1150
1. X can be VIL or VIH, but no other value.
©2005 Silicon Storage Technology, Inc.
S71150-09-000
1/06
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