512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
CE#
OE#
WE#
T
CE
T
OE
T
T
OHZ
V
OLZ
IH
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
1150 F03.0
Note:
A
MS
A
MS
= Most significant address
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
for SST39LF/VF020 and A for SST39LF/VF040
A
18
FIGURE 5: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
MS-0
T
AH
T
DH
T
WP
WE#
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
1150 F04.0
(ADDR/DATA)
Note:
A
MS
A
MS
= Most significant address
= A for SST39LF/VF512, A for SST39LF/VF010,
15
17
16
for SST39LF/VF020 and A for SST39LF/VF040
A
18
FIGURE 6: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71150-09-000
1/06
10
SST [ SILICON STORAGE TECHNOLOGY, INC ]
