512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
PIN DESCRIPTION
Top View
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
RST#/HOLD#
RST#/HOLD#
Top View
WP#
SCK
SI
WP#
SCK
SI
V
SS
V
SS
1328 08-wson P2.0
1328.25WF 08-soic-P0.0
8-Contact WSON
8-Lead SOIC
FIGURE 2: Pin Assignment for 8-Lead SOIC and 8-Contact WSON
TABLE 1: Pin Description
Symbol
Pin Name
Functions
To provide the timing of the serial interface.
SCK
Serial Clock
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 14 for more information.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
Reset
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
RST#/HOLD#
Hold
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence which is detailed in “Reset/Hold
Mode” on page 5.
VDD
VSS
Power Supply
Ground
To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020/040
T1.0 1328
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
