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SST25WF040-40-5I-QAF 参数 Datasheet PDF下载

SST25WF040-40-5I-QAF图片预览
型号: SST25WF040-40-5I-QAF
PDF下载: 下载PDF文件 查看货源
内容描述: 512千位/ 1兆位/ 2兆位/ 4Mbit的1.8V SPI串行闪存 [512 Kbit / 1 Mbit / 2 Mbit / 4Mbit 1.8V SPI Serial Flash]
分类和应用: 闪存
文件页数/大小: 32 页 / 882 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Block-Protection (BP2, BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area to be software protected against any mem-
ory Write (Program or Erase) operation, see Tables 5-7.
The Write-Status-Register (WRSR) instruction is used to
program the BP1 and BP0 bits as long as WP# is high or
the Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only
be executed if Block-Protection bits are all ‘0’. After power-
up, BP2, BP1, and BP0 are set to defaults. See Table 4 for
defaults at power-up.
Block Protection Lock-Down (BPL)
When the WP# pin is driven low (V
IL
), it enables the Block-
Protection-Lock-Down (BPL) bit. When BPL is set to ‘1’, it
prevents any further alteration of the BPL, BP1, and BP0
bits. When the WP# pin is driven high (V
IH
), the BPL bit
has no effect and its value is ‘Don’t Care’. After power-up,
the BPL bit is reset to ‘0’.
TABLE 5: Software Status Register Block Protection for SST25WF512
Status Register Bit
Protection Level
None
1 (Upper Quarter Memory)
2 (Upper Half Memory)
3 (Full Memory)
1. Default at power-up for BP1 and BP0 is ‘11’.
Protected Memory Address
512 Kbit
None
00C000H-00FFFFH
008000H-00FFFFH
000000H-00FFFFH
T5.1 1328
BP1
1
0
0
1
1
BP0
0
1
0
1
TABLE 6: Software Status Register Block Protection for SST25WF010
Status Register Bit
Protection Level
None
1 (Upper Quarter Memory)
2 (Upper Half Memory)
3 (Full Memory)
1. Default at power-up for BP1 and BP0 is ‘11’.
Protected Memory Address
1 Mbit
None
018000H-01FFFFH
010000H-01FFFFH
000000H-01FFFFH
T6.0 1328
BP1
1
0
0
1
1
BP0
0
1
0
1
TABLE 7: Software Status Register Block Protection for SST25WF020
Status Register Bit
Protection Level
None
1 (Upper Quarter Memory)
2 (Upper Half Memory)
3 (Full Memory)
1. Default at power-up for BP1 and BP0 is ‘11’.
Protected Memory Address
2 Mbit
None
030000H-03FFFFH
020000H-03FFFFH
000000H-03FFFFH
T7.0 1328
BP1
1
0
0
1
1
BP0
0
1
0
1
©2009 Silicon Storage Technology, Inc.
S71328-08-000
11/09
8