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SST25VF064C-80-4I-Q2AE 参数 Datasheet PDF下载

SST25VF064C-80-4I-Q2AE图片预览
型号: SST25VF064C-80-4I-Q2AE
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位的SPI串行双I / O闪存 [64 Mbit SPI Serial Dual I/O Flash]
分类和应用: 闪存
文件页数/大小: 31 页 / 903 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the Memory Write protection. During an internal Erase or
TABLE 4: Status Register
Bit
0
1
2
3
4
5
6
Name
BUSY
WEL
BP0
BP1
BP2
BP3
SEC
1
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Indicate current level of block write protection (See Table 5)
Security ID status
1 = Security ID space locked
0 = Security ID space not locked
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are readable/writable
Default at
Power-up
0
0
1
1
1
1
0
1
Read/Write
R
R
R/W
R/W
R/W
R/W
R
Program operation, the status register may be read only to
determine the completion of an operation in progress.
status register.
7
BPL
0
R/W
T4.0 1392
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; otherwise, the
default at power up is ‘0’.
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A ‘1’ for the Busy bit indi-
cates the device is busy with an operation in progress. A ‘0’
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
Power-up
Write-Disable (WRDI) instruction completion
Write-Status Register instruction completion
Page-Program instruction completion
Dual-Input Page-Program instruction completion
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Program SID instruction completion
Lockout SID instruction completion
S71392-04-000
04/10
©2010 Silicon Storage Technology, Inc.
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