4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status regis-
ter. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
19 for EWSR or WREN and WRSR instruction sequences.
BPL bit is disabled and the BPL, BP0, and BP1 and BP2
bits in the status register can all be changed. As long as
BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the
low-to-high transition of the CE# pin at the end of the
WRSR instruction, the bits in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0, BP1, and
BP2 bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”. When
the WP# is low, the BPL bit can only be set from “0” to “1” to
lock-down the status register, but cannot be reset from “1”
to “0”. When WP# is high, the lock-down function of the
CE#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE 3
MODE 0
MODE 3
MODE 0
SCK
STATUS
REGISTER IN
50 or 06
01
7 6 5 4 3 2 1 0
MSB
SI
MSB
MSB
HIGH IMPEDANCE
SO
1295 EWSR.0
FIGURE 19: Enable-Write-Status-Register (EWSR) or
Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
©2009 Silicon Storage Technology, Inc.
S71295-05-000
10/09
19
SST [ SILICON STORAGE TECHNOLOGY, INC ]
