4 Mbit SPI Serial Flash
SST25VF040B
Data Sheet
CE#
SCK
MODE 3
MODE 0
0
1 2 3 4 5 6 7
06
SI
MSB
HIGH IMPEDANCE
SO
1295 WREN.0
FIGURE 17: Write Enable (WREN) Sequence
Write-Disable (WRDI)
terminate any programming operation in progress. Any pro-
gram operation in progress may continue up to TBP after
executing the WRDI instruction. CE# must be driven high
before the WRDI instruction is executed.
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. The WRDI instruction will not
CE#
MODE 3
0
1
2
3
4 5 6 7
MODE 0
SCK
04
SI
MSB
HIGH IMPEDANCE
SO
1295 WRDI.0
FIGURE 18: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-Status-
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruc-
tion followed by the WRSR instruction works like SDP (soft-
ware data protection) command structure which prevents
any accidental alteration of the status register values. CE#
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
©2009 Silicon Storage Technology, Inc.
S71295-05-000
10/09
18
SST [ SILICON STORAGE TECHNOLOGY, INC ]
