FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
TABLE 14-10: SERIAL PORT TIMING
Oscillator
12MHz
40MHz
Variable
Symbol Parameter
Min Max Min Max
Min
Max
Units
µs
TXLXL
TQVXH
TXHQX
Serial Port Clock Cycle Time
1.0
700
50
0.3
12TCLCL
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
117
10TCLCL - 133
2TCLCL - 117
2TCLCL - 50
0
ns
ns
0
0
ns
TXHDX
TXHDV
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
0
ns
700
117
10TCLCL - 133
ns
T14-10.0 1255
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
T
XLXL
CLOCK
T
XHQX
T
QVXH
0
1
2
3
4
5
6
7
OUTPUT DATA
T
XHDX
T
SET TI
WRITE TO SBUF
INPUT DATA
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET R I
CLEAR RI
1255 F39.0
FIGURE 14-7: SHIFT REGISTER MODE TIMING WAVEFORMS
V
+0.1V
-0.1V
V
LOAD
IHT
V
V
-0.1V
OH
V
HT
Timing Reference
Points
V
LOAD
V
V
+0.1V
LT
OL
LOAD
V
ILT
1255 F41.0
1255 F40.0
For timing purposes, a port pin is no longer floating when a 100 mV
change from load voltage occurs, and begins to float when a 100 mV
AC Inputs during testing are driven at V
(V
-0.5V) for Logic "1" and
IHT DD
V
(0.45V) for a Logic "0". Measurement reference points for inputs and
ILT
outputs are at V
change from the loaded V /V
level occurs. I /I = ± 20mA.
(0.2V
+ 0.9) and V (0.2V
- 0.1)
OH OL
OL OH
HT
DD LT
DD
Note: V - V
Test
Test
HIGH Test
LOW Test
HT HIGH
V
V
V
- V
-V
LT
LOW
IHT INPUT
- V
ILT INPUT
FIGURE 14-8: AC TESTING INPUT/OUTPUT TEST
WAVEFORM
FIGURE 14-9: FLOAT WAVEFORM
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
79
SST [ SILICON STORAGE TECHNOLOGY, INC ]
