FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
1
TABLE 14-11: EXTERNAL MODE FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS
Parameter2,3
Symbol
TSU
Min
3
Max
Units
µs
Reset Setup Time
Read-ID Command Width
PSEN# Setup Time
TRD
1
µs
TES
40
0
µs
Address, Command, Data Setup Time
Chip-Erase Time
TADS
TCE
ns
150
100
30
ms
ms
ms
µs
Block-Erase Time
TBE
Sector-Erase Time
TSE
Program Setup Time
TPROG
TDH
1.2
0
Address, Command, Data Hold
Byte-Program Time4
ns
TPB
50
500
80
µs
Select-Block Program Time
Re-map or Security bit Program Time
Verify Command Delay Time
Verify High Order Address Delay Time
Verify Low Order Address Delay Time
TPSB
TPS
ns
µs
TOA
50
ns
TAHA
TALA
50
ns
50
ns
T14-11.0 1255
1. For IAP operations, the program execution overhead must be added to the above timing parameters.
2. Program and Erase times will scale inversely proportional to programming clock frequency.
3. All timing measurements are from the 50% of the input to 50% of the output.
4. Each byte must be erased before programming.
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
81
SST [ SILICON STORAGE TECHNOLOGY, INC ]
