FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
SuperFlash Data Register (SFDT)
Location
7
6
5
4
3
2
1
0
Reset Value
B5H
SuperFlash Data Register
00H
Symbol
Function
SFDT
Mailbox register for interfacing with flash memory block. (Data register).
SuperFlash Status Register (SFST) (Read Only Register)
Location
7
6
5
4
3
2
1
0
Reset Value
FLASH_BUSY
B6H
SB1_i
SB2_i
SB3_i
-
EDC_i
-
-
xxxxx0xxb
Symbol
SB1_i
SB2_i
SB3_i
Function
Security Bit 1 status (inverse of SB1 bit)
Security Bit 2 status (inverse of SB2 bit)
Security Bit 3 status (inverse of SB3 bit)
Please refer to Table 9-1 for security lock options.
EDC_i
Double Clock Status
0: 12 clocks per machine cycle
1: 6 clocks per machine cycle
FLASH_BUSY Flash operation completion polling bit.
0: Device has fully completed the last IAP command.
1: Device is busy with flash operation.
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
23
SST [ SILICON STORAGE TECHNOLOGY, INC ]
