W150
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.8 MHz
Min. Typ. Max. Min. Typ. Max. Unit
CPU = 100 MHz
Parameter
tD
Description
Duty Cycle
Test Condition/Comments
Measured on rising and falling edge at
1.5V
45
55
45
55
ꢀ
tSK
Output Skew
Measured on rising and falling edge at
1.5V
250
250
ps
tPD
Zo
Propagation Delay
Measured from SDRAMIN
3.7
15
3.7
15
ns
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
:
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Min. Typ. Max. Unit
Parameter
Description
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
f
Frequency, Actual
48.008
+167
MHz
ppm
fD
Deviation from 48 MHz (48.008 – 48)/48
m/n
tR
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
0.5
45
2
2
V/ns
V/ns
ꢀ
tF
Output Fall Edge Rate
Duty Cycle
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
ms
from Power-up (cold
start)
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
25
:
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
24.004
+167
Max.
Unit
MHz
ppm
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
fD
Deviation from 24 MHz (24.004 – 24)/24
m/n
tR
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
2
2
V/ns
V/ns
ꢀ
tF
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
ms
from Power-up (cold
start)
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
25
:
Layout Example
Rev 1.0,November 24, 2006
Page 12 of 14