W150
DC Electrical Characteristics (TA = 0°C to +70°C; VDDQ3 = 3.3V 5ꢀ; VDDQ2 = 2.5V 5ꢀ) (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input threshold Voltage[6]
VDDQ3 = 3.3V
1.65
14
V
CLOAD
Load Capacitance, Imposed on
External Crystal[7]
pF
CIN,X1
X1 Input Capacitance[8]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
COUT
LIN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V 5ꢀ; VDDQ2 = 2.5V 5ꢀ; fXTL
= 14.31818 MHz. AC clock parameters are tested and
guaranteed over stated operating conditions using the stated
lump capacitive load at the clock output; Spread Spectrum
clocking is disabled.
CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
tP
Description
Period
Test Condition/Comments
Measured on rising edge at 1.25
Duration of clock cycle above 2.0V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
15
5.2
5.0
1
15.5
10
3.0
2.8
1
10.5
ns
ns
tH
tL
High Time
Low Time
ns
tR
tF
tD
Output Rise Edge Rate Measured from 0.4V to 2.0V
Output Fall Edge Rate Measured from 2.0V to 0.4V
4
4
4
4
V/ns
V/ns
ꢀ
1
1
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
250
250
ps
tSK
fST
Output Skew
Measured on rising edge at 1.25V
175
3
175
3
ps
Frequency Stabilization Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
ms
from Power-up (cold
start)
Zo
AC Output Impedance Average value during switching
transition. Used for determining series
termination value.
20
20
:
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100 MHz
Min. Typ. Max.
30
Parameter
tP
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Unit
Period
ns
ns
tH
tL
High Time
12.0
12.0
1
Low Time
ns
tR
Output Rise Edge Rate
4
V/ns
Notes:
6. X1 input threshold voltage (typical) is V
/2.
DDQ3
7. The W150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
Rev 1.0,November 24, 2006
Page 10 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
