W150
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)
CPU = 66.6/100 MHz
Parameter
tD
Description
Duty Cycle
Test Condition/Comments
Min.
Typ.
Max.
55
Unit
ꢀ
Measured on rising and falling edge at 1.5V
45
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
250
ps
tSK
tO
Output Skew
Measured on rising edge at 1.5V
500
4
ps
ns
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
fST
Frequency Stabilization
Assumes full supply voltage reached within
3
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior
to frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
:
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
ꢀ
f
14.31818
tR
1
1
4
4
tF
Measured from 2.0V to 0.4V
tD
Measured on rising and falling edge at 1.25V
45
55
1.5
fST
Frequency Stabilization
Assumes full supply voltage reached within
ms
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15
:
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ. Max.
Unit
MHz
V/ns
V/ns
ꢀ
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
0.5
0.5
45
2
2
tF
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
ms
from Power-up (cold
start)
Zo
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
25
:
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)
CPU = 66.8 MHz
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Min. Typ. Max. Min. Typ. Max. Unit
t
15
5.2
5.0
1
15.5
10
3.0
2.0
1
10.5
ns
ns
P
tH
High Time
Low Time
tL
tR
tF
ns
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
4
4
4
4
V/ns
V/ns
1
1
Rev 1.0,November 24, 2006
Page 11 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
