W320-03
[1]
Function Table
CPU
(MHz)
3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5 PCI_F/PCI
(MHz)
USB/DOT
(MHz)
S2 S1
S0
(MHz)
V66[2:4] (MHz)
(MHz)
REF0(MHz)
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66 MHz
66 MHz
66 IN
66 MHz Input 66 IN/2
66 MHz Input 66 IN/2
66 MHz Input 66 IN/2
66 MHz Input 66 IN/2
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
1
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
66 IN
1
66 IN
1
66 IN
0
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
0
100 MHz 66 MHz
200 MHz 66 MHz
133 MHz 66 MHz
0
0
Mid
Mid
Mid
Mid
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TCLK/2
TCLK/4
TCLK/4
TCLK/4
Reserved
Reserved
TCLK/8
Reserved
Reserved
TCLK
TCLK/2
Reserved
Reserved
6, 7, 8
–
Reserved Reserved Reserved
Reserved Reserved Reserved
Reserved
Reserved
–
Swing Select Functions
Board Target
Trace/Term Z
Reference R, IREF =
VDD/(3*Rr)
Output
Current
Mult0
VOH @ Z
0
60:
Rr = 221 1%,
IREF = 5.00 mA
I
OH = 4*IREF
1.0V @ 50
1
50:
Rr = 475 1%,
IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Clock Driver Impedances
Impedance
Minimum
:
Typical
:
Maximum
:
Buffer Name
CPU, CPU#
VDD Range
Buffer Type
Type X1
Type 3
50
40
30
30
30
REF
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
20
12
12
12
60
55
55
55
PCI, 3V66, 66BUFF
Type 5
USB
DOT
Type 3A
Type 3B
Clock Enable Configuration
VCOS/
PWR_DWN# CPU_STOP# PCI_STOP#
CPU
CPU# 3V66 66BUFF PCI_F PCI USB/DOT
OSC
OFF
ON
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
IREF*2 FLOAT LOW
LOW
ON
LOW LOW
LOW
ON
IREF*2 FLOAT
IREF*2 FLOAT
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
Notes:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation.
3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
6. TCLK is a test clock over driven on the XTAL_IN input during test mode.
7. Required for DC output impedance verification.
8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Rev 1.0,November 25, 2006
Page 3 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
