W305B
Group Skew and Jitter Limits
Skew, Jitter
Output Group
CPU
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom Vdd
2.5V
Measure Point
1.25V
1.5V
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
SDRAM
APIC
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
48MHz
3V66
500 ps
45/55
3.3V
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
T
PERIOD
Duty Cycle
T
HIGH
2.0
1.25
0.4
2.5V Clocking
Interface
T
LOW
T
T
RISE
FALL
T
PERIOD
Duty Cycle
T
HIGH
2.4
1.5
0.4
3.3V Clocking
Interface
T
LOW
T
T
RISE
FALL
Figure 6. Output Buffer
Layout Example
Rev 1.0,November 20, 2006
Page 18 of 20