W305B
AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5%fXTL = 14.31818 MHz[2]
66.6-MHz Host 100-MHz Host 133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit
ns
ns 4,7
Notes
4
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
TLOW
5.0
2.8
ns
ns
ns
5
TRISE
0.4
0.4
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
4
4
5
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC CLK Period
60.0
25.5
25.3
0.4
64.0
N/A
N/A
1.6
60.0
25.5
25.30
0.4
N/A
N/A
N/A
1.6
60.0
25.5
25.30
0.4
64.0
N/A
N/A
1.6
ns
ns
ns
ns
ns
4
4
5
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns 4, 5
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
ns
ns
ns
ns
4
5
0.5
2.0
0.5
2.0
0.5
2.0
TPeriod
THIGH
TLOW
TRISE
TFALL
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
ns 4, 7
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
ns
ns
ns
ns
4
5
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
1.0
1.0
10.0
10.0
1.0
1.0
10.0
10.0
1.0
1.0
10.0
10.0
ns
ns
Output Disable Delay
(All outputs)
tstable
All Clock Stabilization from
Power-Up
3
3
3
ms
Notes:
4. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when V achieves its nominal operating level (typical condition V
operating within specification.
= 3.3V) until the frequency output is stable and
DDQ3
DDQ3
6. T
7. T
8. T
and T
are measured as a transition through the threshold region V = 0.4V and V = 2.0V (1 mA) JEDEC specification.
RISE
LOW
HIGH
FALL ol oh
is measured at 0.4V for all outputs.
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
Rev 1.0,November 20, 2006
Page 17 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
