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CY2SSTU32866 参数 Datasheet PDF下载

CY2SSTU32866图片预览
型号: CY2SSTU32866
PDF下载: 下载PDF文件 查看货源
内容描述: 1.8V , 25位( 1 : 1 ) 14位( 1 : 2 ) JEDEC兼容的数据寄存器与校验 [1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity]
分类和应用:
文件页数/大小: 24 页 / 236 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2SSTU32866  
Pin Definition (continued)  
Pin Number  
(C0 = 0, C1 = 0)  
Pin Number  
(C0 = 0, C1 = 1)  
Pin Number  
(C0 = 1, C1 = 1)  
Pin Name  
Description  
RESET#  
G2  
G2  
G2  
Asynchronous reset – resets registers and  
disables Vref data and clock differential input  
receivers  
CSR#  
DCS#  
D1  
J2  
J2  
J2  
ChipSelectDisablesD1-D24whenbothCSR#  
and DCS# are HIGH (VDD  
ChipSelectDisablesD1-D24whenbothCSR#  
and DCS# are HIGH (VDD  
)
H2  
H2  
H2  
)
A1  
Data input – clocked in on the crossing points of  
CK and CK#  
D2-3  
D4  
B1, C1  
B1, C1  
B1, C1  
D1  
Data input – clocked in on the crossing points of  
CK and CK#  
Data input – clocked in on the crossing points of  
CK and CK#  
D5, 6, 8, 9, E1, F1, K1, L1, M1  
10  
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of  
CK and CK#  
D11  
N1  
N1  
Data input – clocked in on the crossing points of  
CK and CK#  
D12, 13  
D14  
P1, R1  
T1  
P1, R1  
T1  
P1, R1  
Data input – clocked in on the crossing points of  
CK and CK#  
Data input – clocked in on the crossing points of  
CK and CK#  
D15-25  
DODT  
DCKE  
Q1A  
B2, C2, E2, F2, K2, L2,  
M2, N2, P2, R2, T2  
Data input – clocked in on the crossing points of  
CK and CK#  
D1  
D1  
A1  
N1  
The outputs of this register bit will not be  
suspended by the DCS# and CSR# Control  
A1  
T1  
The outputs of this register bit will not be  
suspended by the DCS# and CSR# Control  
A5  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Q2A-3A  
Q4A  
B5, C5  
B5, C5  
B5, C5  
D5  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Q5A,6A,8A, E5, F5, K5, L5, M5  
9A, 10A  
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#  
and CSR# control  
Q11A  
N5  
N5  
Q12A, Q13A P5, R5  
P5, R5  
T5  
P5, R5  
Q14A  
Q1B  
T5  
Data Outputs that are suspended by the DCS#  
and CSR# control  
A6  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Q2B-3B  
Q4B  
B6, C6  
B6, C6  
D6  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Q5B,6B,8B,  
9B, 10B,  
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#  
and CSR# control  
Q11B  
N6  
Data Outputs that are suspended by the DCS#  
and CSR# control  
Rev 1.0,November 25, 2006  
Page 3 of 24