CY28447
Pin Description
Pin No.
Name
Type
Description
1, 49, 54, 65 VDD_SRC
PWR 3.3V power supply for outputs.
2, 3, 50, 51, SRCT/C[1:9]
52, 53, 55,
56, 58, 59,
O, DIF 100 MHz Differential serial reference clocks.
60, 61, 63,
64, 66, 67,
69, 70
4, 68
5, 6
VSS_SRC
GND Ground for outputs.
CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.
ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
CPUC2_ITP/SRCC10
7
8
9
VDDA
VSSA
IREF
PWR 3.3V power supply for PLL.
GND Ground for PLL.
I
A precision resistor is attached to this pin which is connected to the internal
current reference.
10, 11, 13, 14 CPUT/C[0:1]
O, DIF Differential CPU clock outputs.
PWR 3.3V power supply for outputs.
GND Ground for outputs.
12
15
16
17
18
19
20
21
22
23
VDD_CPU
VSS_CPU
SCLK
I
SMBus-compatible SCLOCK.
SDATA
VDD_REF
XOUT
I/O, OD SMBus-compatible SDATA.
PWR 3.3V power supply for outputs.
O, SE 14.318 MHz crystal output.
XIN
I
14.318 MHz crystal input.
GND Ground for outputs.
Fixed 14.318 MHz clock output.
VSS_REF
REF1
O
REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is
asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24
25
CPU_STP#
PCI_STP#
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
I, PU 3.3V LVTTL input for PCI_STP# active LOW.
26, 28, 29,
38, 46, 57,
62, 71, 72
CLKREQ[1:9]#
I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW).
27, 32, 33
30, 36
31, 35
34
PCI[1:3]
O, SE 33 MHz clock outputs
PWR 3.3V power supply for outputs.
GND Ground for outputs.
VDD_PCI
VSS_PCI
PCI4/FCTSEL1
I/O, PD 33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 Pin 43
0 DOT96T
Pin 44
DOT96C
27M_SS
Pin 47
Pin 48
96/100M_T 96/100M_C
SRCT0 SRCC0
1 27M_NSS
37
ITP_SEL/PCIF0
I/O,PD, 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10
SE
Rev 1.0,November 20, 2006
Page 2 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
