CY28447
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
1
0
CPU[T/C]1
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
5
4
3
0
1
1
1
TEST_MODE
REF1
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
REF1 Output Drive Strength
0 = Low, 1 = High
REF0
REF0 Output Drive Strength
0 = Low, 1 = High
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert
to free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FSC
FSB
FSA
FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit @Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 1
Vendor ID Bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
Description
RESERVED, Set = 0
7
6
5
4
3
2
0
0
0
0
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
USB_48M
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
USB_48MHz Output Drive Strength
0= Low, 1= High
1
0
1
1
RESERVED
PCIF0
RESERVED, Set = 1
PCIF0 Output Drive Strength
0 = Low, 1 = High
Rev 1.0,November 20, 2006
Page 7 of 21