CY28447
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
SRC[T/C]7
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0
/LCD_96_100M[T/C]
SRC[T/C]0 / LCD_96_100M[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
0
27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48MHz
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
REF0
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1
CPU[T/C]0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Spread Enable
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
PCI3
PCI2
PCI1
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
3
2
1
1
1
1
Reserved
Reserved
CPU[T/C]2
Reserved, Set = 1
Reserved, Set = 1
CPU[T/C]2 Output Enable
0 = Disabled (Hi-Z), 1 = Enabled
0
1
Reserved
Reserved, Set = 1
Rev 1.0,November 20, 2006
Page 5 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
