CY28405
Byte 10: Control Register 10 (continued)
Bit
1
@Pup
Name
Description
Description
1
1
Reserved
Reserved
Reserved, Set = 1
Reserved, Set = 1
0
Byte 11: Control Register 11
Bit
7
@Pup
Name
0
0
Reserved
Vendor Test Mode (always program to 0)
6
Recovery_Frequency
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use Hardware settings
1: Use Last SW table Programmed values
5
4
0
0
Watchdog Time Stamp
Reload
Toenablethis function theregister bit mustfirst beset to“0”before toggling
to “1”.
0: Do not reload
1: Reset timer but continue to count.
WD_Alarm
This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
3
2
1
0
0
0
0
0
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
Watchdog timer time stamp selection:
0000: Off
0001: 2 second
0010: 4 seconds
0011: 6 seconds
.
.
.
1110: 28seconds
1111: 30seconds
Byte 12: Control Register 12
Bit
7
@Pup
Name
CPU_FSEL_N8
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
Description
0
0
0
0
0
0
0
0
If Prog_Freq_EN isset, the values programmed inCPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
6
5
4
3
2
1
0
Byte 13: Control Register 13
Bit
7
@Pup
Name
CPU_FSEL_N0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
Description
0
0
0
0
0
0
0
0
IfProg_Freq_ENisset, thevaluesprogrammedinCPU_FSEL_N[8:0]and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
6
5
4
3
2
1
0
Rev 1.0,November 20, 2006
Page 9 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
