CY28405
Byte 2: Control Register 2
Bit
7
@Pup
Name
Description
0
0
0
Reserved
Reserved
Reserved, set = 0
Reserved, set = 0
6
5
CPUT_ITP, CPUC_ITP
CPUT/C_ITP Pwrdwn drive mode
0 = Driven in power- down, 1 = three-state
4
3
0
0
CPUT1, CPUC1
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
CPUT0, CPUC0
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
2
1
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume
in a synchronous manner with no short pulses.
6
5
1
1
Reserved
PCI5
Reserved
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
3
2
1
0
1
1
1
1
1
PCI4
PCI3
PCI2
PCI1
PCI0
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
USB_48
(404: 24_48MHz)
USB 48 (404: and 24MHz) Drive Strength Control
0 = High Drive Strength, 1 = Low Drive Strength
6
5
4
3
2
1
0
1
0
0
0
1
1
1
USB_48
PCIF2
PCIF1
PCIF0
PCIF2
PCIF1
PCIF0
USB_48 Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 20, 2006
Page 6 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
