CY28405
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms. The
CPUT/C outputs must be driven to greater than 200 mV is less
than 300 Ps.
Tstable
<1.8ms
PWRDWN#
CPUT, 133MHz
CPUC, 133MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PWRDN#
<300Ps, >200mV
Figure 4. Power-down Deassertion Timing Waveforms
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. VTT_PWRGD Timing Diagram
Rev 1.0,November 20, 2006
Page 12 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
