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CY28405OXC 参数 Datasheet PDF下载

CY28405OXC图片预览
型号: CY28405OXC
PDF下载: 下载PDF文件 查看货源
内容描述: CK409兼容的时钟合成器 [CK409-Compliant Clock Synthesizer]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 18 页 / 198 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28405  
PD# Deassertion  
The power-up latency between PD# rising to a valid logic ‘1’  
level and the starting of all clocks is less than 1.8 ms. The  
CPUT/C outputs must be driven to greater than 200 mV is less  
than 300 Ps.  
Tstable  
<1.8ms  
PWRDWN#  
CPUT, 133MHz  
CPUC, 133MHz  
3V66, 66MHz  
USB, 48MHz  
PCI, 33MHz  
REF, 14.31818  
Tdrive_PWRDN#  
<300Ps, >200mV  
Figure 4. Power-down Deassertion Timing Waveforms  
FS_A, FS_B  
VTT_PWRGD#  
PWRGD_VRM  
0.2-0.3mS  
Delay  
Wait for  
VTT_PWRGD#  
Device is not affected,  
VTT_PWRGD# is ignored  
Sample Sels  
State 2  
VDD Clock Gen  
Clock State  
State 0  
Off  
State 1  
State 3  
On  
Clock Outputs  
Clock VCO  
On  
Off  
Figure 5. VTT_PWRGD Timing Diagram  
Rev 1.0,November 20, 2006  
Page 12 of 18