CY28405
Table 9. Maximum Lumped Capacitive Output Loads
Test and Measurement Set-up
Clock
Max Load
Units
pF
For Differential CPU and SRC Output Signals
PCI Clocks
3V66 Clocks
USB Clock
DOT Clock
REF Clock
30
30
20
10
30
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
pF
pF
pF
pF
M easurem ent
Point
2pF
TPCB
ꢀꢀ:
CPUT
ꢁꢂꢃꢂ:
M easurem ent
Point
2pF
TPCB
ꢀꢀ:
CPUC
IREF
ꢁꢂꢃꢂ:
ꢁꢄꢅ:
Figure 7. 0.7V Load Configuration
O u tp u t u nd e r T e st
P ro b e
L o a d C a p
3 .3 V s ig n a ls
tD C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0 V
T r
T f
Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameter Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, IREF – VDD (3*RREF
)
Output Current
VOH @ Z
50 Ohms
RREF = 475 1%, IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Rev 1.0,November 20, 2006
Page 17 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
