CY28352
Maximum Ratings[3]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD:............ VDD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +70°C
Maximum Power Supply:................................................3.5V
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDDA = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C[4]
Parameter
VIL
Description
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Condition
SDATA, SCLK
Min.
Typ.
Max.
Unit
V
1.0
VIH
SDATA, SCLK
CLKIN, FBIN
CLKIN, FBIN
2.2
V
VIL
0.4
10
V
VIH
2.1
V
IIN
VIN = 0V or VIN = VDDQ, CLKIN,
FBIN
–10
µA
Input Current
IOL
IOH
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[5]
Output Crossing Voltage[6]
V
DDQ = 2.375V, VOUT = 1.2V
26
35
mA
mA
V
VDDQ = 2.375V, VOUT = 1V
VDDQ = 2.375V, IOL = 12 mA
VDDQ = 2.375V, IOH = –12 mA
–18
–32
VOL
VOH
VOUT
VOC
IOZ
0.6
1.7
1.1
V
VDDQ – 0.4
(VDDQ/2) + 0.2
10
V
(VDDQ/2) – 0.2 VDDQ/2
–10
V
High-Impedance Output
Current
µA
VO = GND or VO = VDDQ
IDDQ
[7] All VDDQ and VDDI
,
235
300
mA
Dynamic Supply Current
FO = 170 MHz
IDSTAT Static Supply Current
1
12
6
mA
mA
pF
IDD
Cin
PLL Supply Current
VDDA only
9
4
Input Pin Capacitance
[7, 9]
AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C
Parameter
fCLK
Description
Operating Clock Frequency
Input Clock Duty Cycle
Condition
Min.
60
Typ. Max.
Unit
MHz
%
200
60
tDC
40
tlock
Tr / Tf
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time[10]
(all outputs)
Output Disable Time[10]
(all outputs)
Cycle-to-Cycle Jitter[12]
Half-period jitter[12]
100
2.5
μs
20% to 80% of VOD
1
V/ns
tpZL, tpZH
3
3
ns
ns
tpLZ, tpHZ
tCCJ
f > 66 MHz
f > 66 MHz
–100
–100
100
100
ps
ps
tjit(h-per)
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see Figure 7.
6. The value of V is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7.
OC
7. All outputs switching loaded with 16 pF in 60Ω environment. SeeFigure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down
spread of –0.5%.
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other.
Rev 1.0,November 21, 2006
Page 4 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
