CY28352
Pin Description[1]
Electrical
Pin Number Pin Name
I/O
Pin Description
Complementary Clock Input.
Characteristics
8
CLKIN
I
Input
Feedback Clock Input. Connect to FBOUT for accessing the Input
PLL.
20
FBIN
I
2,4,13,17,24,
26
Clock Outputs
Differential Outputs
CLKT(0:5)
CLKC(0:5)
O
O
1,5,14,16,25,
27
Clock Outputs
Feedback Clock Output. Connect to FBIN for normal operation. Output
A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
19
7
FBOUT
SCLK
O
I
Serial Clock Input. Clocks data at SDATA into the internal
Data Input for the two line
serial bus
register.
Serial Data Input. Input data is clocked to the internal register to Data Input and Output for
22
SDATA
I/O enable/disable individual outputs. This provides flexibility in
power management.
the two line serial bus
3,12,23
10
VDD
AVDD
GND
AGND
NC
2.5V Power Supply for Logic
2.5V Power Supply for PLL
Ground
2.5V Nominal
2.5V Nominal
6,15,28
11
Analog Ground for PLL
Not Connected
9, 18, 21
Zero Delay Buffer
Power Management
When used as a zero delay buffer the CY28352 will likely be
in a nested clock tree application. For these applications the
CY28352 offers a clock input as a PLL reference. The
CY28352 can then lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
The individual output enable/disable control of the CY28352
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set low in Byte0 and Byte1 registers. The feedback output
FBOUT cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Function Table
Inputs
Outputs
CLKC(0:5)[2]
PLL
VDDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
CLKT(0:5)[2]
FBOUT
L
L
H
H
L
L
H
BYPASSED/OFF
H
BYPASSED/OFF
L
H
L
H
L
On
On
Off
H
L
H
<20 MHz
Hi-Z
Hi-Z
Hi-Z
Notes:
1. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
Rev 1.0,November 21, 2006
Page 2 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
