CY28349B
Layout Example
+3.3V Supply
FB
VDDQ3
0.005PF
C3
G
G
1
48
47
46
45
G
G
G
V
2
3
4
5
6
7
8
9
V
G
G
G
G
44
43
42
41
40
39
38
37
36
35
34
3
G
V
G
G
G
V
G
10
11
12
G
G
G
G
13
14
15
16
17
18
19
20
V
G
G
V
G
32
G
G 31
30
G
V
G
G
29
G
21
22
23
24
28
27
26
VDDQ3
5:
G
G
*
25
C6
G
C5
G
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz)
C5 = 10 PF C6 = 0.1 PF
PF
C4 = 0.005
PF
Ceramic Caps C3 = 10–22
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 PF ceramic
* For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3
Rev 1.0,November 20, 2006
Page 19 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
