CY28347
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The setup
time for capturing PCI_STP# going LOW is 10 ns (tsetup). The
PCI_F clock will not be affected by this pin.
t setup
PCI_STP#
PCI_F
PCI(1:6)
Figure 11. PCI_STP# Assertion Waveform
PCI_STP#- Deassertion
The deassertion of the PCI_STP# signal will cause all PCI
clocks to resume running in a synchronous manner within one
PCI clock period after PCI_STP# transitions to a HIGH level.
t setup
PCI_STP#
PCI_F
PCI(1:6)
Figure 12. PCI_STP# Deassertion Waveform
Power Management Functions
Power Down Assertion (P4 Mode)
All clocks can be individually enabled or stopped via the 2-wire
control interface. All clocks maintain valid HIGH period on
transitions from running to stop and on transitions from
stopped to running when the chip was not powered OFF.
When PD# is sampled LOW by two consecutive rising edges
of CPUC clock then all clocks must be held LOW on their next
HIGH to LOW transition. CPUT clocks must be held with a
value of 2 x Iref,
Rev 1.0,November 20, 2006
Page 17 of 21
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