CY28347
CPU_STP# Assertion (P4 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by two rising CPUC clock edges.
The final state of the stopped CPU signal is CPUT = HIGH and
CPUC = LOW. There is no change to the output drive current
values during the stopped state. The CPUT is driven HIGH
with a current value equal to (Mult 0 “select”) x (Iref), and the
CPUC signal will not be driven. Due to external pulldown
circuitry CPUC will be LOW during this stopped state.
CPU_STP#
CPUT
CPUC
Figure 7. CPU_STP# Assertion Waveform (P4 Mode)
Table 13.CPU_STP# Functionality
CPU_STP# Deassertion (P4 Mode)
CPU_STP#
CPU#4
Normal
Iref*Mult
CPU
Normal
Float
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
1
0
CPU_STP#
CPUT
CPUC
CPUCS_T
CPUCS_C
Figure 8. CPU_STP# Deassertion Waveform (P4 Mode)
Rev 1.0,November 20, 2006
Page 15 of 21
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