CY28347
Maximum Ratings[3]
This device contains circuitry to protect the inputs against
damage due to HIGH static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, VIN and VOUT should be constrained to the
range.
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................ –65qC to + 150qC
Operating Temperature:.................................... 0qC to +70qC
Maximum ESD.............................................................2000V
Maximum Power Supply:................................................5.5V
VSS < (VIN or VOUT) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V 5%, VDDI = VDD = 2.5 5%, TA = 0 °C to +70 °C)
Parameter
VIL1
Description
Input LOW Voltage
Conditions
Min. Typ. Max. Unit
Applicable to PD#, F S(0:4)
1.0
Vdc
Vdc
Vdc
Vdc
V
VIH1
VIL2
VIH2
Vol
Input HIGH Voltage
2.0
Input LOW Voltage
Applicable to SDATA and SCLK
1.0
Input HIGH Voltage
2.2
0.4
24
Output LOW Voltage for Sreset#
Pull-down Current for Sreset#
Three-state Leakage Current
Dynamic Supply Current
Dynamic Supply Current
Power-down Supply current
Internal Pull-up Device Current
Internal Pull-down Device Current
Input Pin Capacitance
IOL
Iol
VOL = 0.4V
35
mA
PA
Ioz
10
180
200
4.0
–25
10
5
Idd3.3V
Idd2.5V
Ipd
CPU frequency set at 133.3[4]
CPU frequency set at 133.3 MHz[4]
PD# = 0
156
177
3.8
mA
mA
mA
PA
Ipup
Ipdwn
Cin
Input @ VSS
Input @ VDD
PA
pF
Cout
Lpin
Cxtal
Output Pin Capacitance
Pin Inductance
6
pF
7
pF
Crystal Pin Capacitance
Measured from the XIN or XOUT to VSS
27
36
45
pF
AC Parameters
66 MHz
100 MHz
133 MHz
200 MHz
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Notes
Crystal
TDC
Xin Duty Cycle
45
55
45
55
45
55
45
55
% 5,6,7,8
ns 5,6,7,8
V 7,9
V
TPeriod
VHIGH
VLOW
Tr / Tf
Xin Period
69.84
71.0
69.84
71.0
69.84
71.0
69.84
71.0
Xin HIGH Voltage
Xin LOW Voltage
Xin Rise and Fall Times
Xin Cycle to Cycle Jitter
Crystal Start-up Time
0.7VDD VDD 0.7VDD VDD 0.7VDD VDD 0.7VDD VDD
0
0.3VDD
10.0
500
0
0.3VDD
10.0
500
0
0.3VDD
10
0
0.3VDD
10
ns 7
TCCJ
500
30
500
30
ps 10,11,12,13
ms 9
Txs
30
30
Notes:
3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All outputs loaded as per maximum capacitative load table in P4 and DDR mode. See Table 12.
5. All outputs loaded as per loading specified in the loading table. See Table 12.
6. This measurement is applicable with Spread ON or spread OFF.
7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8. The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
9. Measured between 0.2Vdd and 0.7Vdd.
10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and between
20% and 80% for differential signals.
11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals.
12. When Xin is driven from and external clock source (3.3V parameters apply).
13. When Crystal meets minimum 40 ohm device series resistance specification.
Rev 1.0,November 20, 2006
Page 9 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
