CY28341
Table 10.Signal Loading Table
Clock Name
Max Load (in pF)
REF (0:1), 48MHz (USB), 24_48MHz
AGP(0:2), SDRAM (0:11)
PCI_F(0:5)
20
30
30
DDRT/C (0:5), FBOUT
CPUT/C
See Figure 10
See Figure 8
See Figure 9
CPUOD_T/C
CPUCS_T/C
For Differential CPU Output Signals (with P4 Processor SELP4_K7= 1)
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
CLK Measurement Point
TPCB
CPUT
RtA1
RtB1
RLA1
RLB1
CLA
RD
MULTSEL
CLK Measurement Point
TPCB
CPUT#
RtA2
RtB2
CLB
RLA2
RLB2
Rref
Figure 10.
Group Timing Relationships and Tolerances[32]
Table 11.Lumped Test Load Configuration
Component 0.7V Amplitude Value 1.0V Amplitude Value
Offset (ps) Tolerance (ps) Conditions
R
tA1, RtA2
RLA1, RLA2
TPCB
LB1, RLB2
RD
tB1, RtB2
LA, CLB
Rref
33:
0:
tCSAGP CPUCSto
AGP
750
500
CPUCS
Leads
49.9:
f
3” 50 :Z
63:
tAP
AGP to
PCI
1,250
500
AGP Leads
3” 50 :Z
R
f
f
470:
R
0:
2 pF
33:
C
2 pF
475: w/mult0 = 1
221: w/mult0 = 0
Note:
32. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), the same
length transmission line to the other signal of the pair (e.g., AGP) should be added.
Rev 1.0,November 20, 2006
Page 17 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
