CY28341
AC Parameters (continued)
100 MHz
133MHz
200 MHz
Parameter
Description
Min.
Max.
Min.
Max
Min.
Max
Unit
Notes[4]
TSKEW
CPUCS_T/C to CPUT/C Clock
Skew
0
200
0
150
0
200
ps 11,15,21,22
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
280
+150
430
–150
280
+150
430
–200
280
+200
430
ps 11,15,21,22
Vcross
Crossing Point Voltage at 0.7V
Swing
mV
22
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
CPUT/C Period
45
55
45
55
45
55
5.1
467
%
nS
ps
11,14,21
11,14,21
13,15,25
TPeriod
9.85
175
10.2
467
7.35
175
7.65
467
4.85
175
Differential CPUT/C Rise and Fall Times
Tr/Tf
TSKEW
CPUCS_T/C to CPUT/C Clock
Skew
0
200
0
150
0
200
0
11,15,21
TCCJ
CPUT/C Cycle to Cycle Jitter
–150
510
+150
760
–150
510
+150
760
–200
510
+200
760
ps
11,15,21
26
Vcross
Crossing Point Voltage at 1V
Swing
mV
SE- Absolute Single-ended Rise/Fall
DeltaSlew Waveform Symmetry
325
325
325
ps
24,31
K7 Mode
TDC
CPUOD_T/C Duty Cycle
CPUOD_T/C Period
45
9.98
2.8
0.4
0
55
45
7.5
1.67
0.4
0
55
45
5
55
%
ns
ns
ns
0
11,14
11,14
TPeriod
TLOW
Tf
10.5
8.0
5.5
CPUOD_T/C LOW Time
CPUOD_T/C Fall Time
2.8
0.4
0
11,14
1.6
1.6
1.6
11,13
TSKEW
CPUCS_T/C to CPUT/C Clock
Skew
200
150
200
11,15,21
TCCJ
CPUOD_T/C Cycle to Cycle
Jitter
–150
+150
–150
+150
–200
+200
ps
11,14
VD
VX
Differential Voltage AC
0.4
Vp+.6V
1100
0.4
Vp+.6V
1100
0.4
Vp+.6V
1100
V
20
19
Differential Crossover Voltage
500
500
500
mV
CHIPSET CLOCK
TDC
TPeriod
Tr / Tf
VD
CPUCS_T/C Duty Cycle
45
10.0
0.4
55
10.5
45
15
55
15.5
45
10.0
0.4
55
10.5
%
ns
ns
V
7,11,14
7,11,14
7,11,13
27
CPUCS_T/C Period
CPUCS_T/C Rise and Fall Times
Differential Voltage AC
1.6
0.4
0.4
1.6
1.6
0.4
Vp+.6V
Vp+.6V
0.4
Vp+.6V
VX
Differential Crossover Voltage
0.5*VDDI 0.5*VDDI + 0.5*VDDI 0.5*VDDI 0.5*VDDI 0.5*VDDI
+ 0.2
V
21
– 0.2
0.2
– 0.2
– 0.2
+ 0.2
AGP
TDC
AGP(0:2) Duty Cycle
45
15
55
16
45
15
55
16
45
15
55
16
%
ns
ns
ns
ns
ps
ps
7,11,14
7,11,14
11,16
TPeriod
THIGH
TLOW
Tr / Tf
AGP(0:2) Period
AGP(0:2) HIGH Time
5.25
5.05
0.4
5.25
5.05
0.4
5.25
5.05
0.4
AGP(0:2) LOW Time
11,17
AGP(0:2) Rise and Fall Times
Any AGP to Any AGP clock Skew
AGP(0:2) Cycle to Cycle Jitter
1.6
250
500
1.6
250
500
1.6
250
500
11,13
TSKEW
TCCJ
11,15
11,14,15
PCI
TDC
PCI(_F,1:6) Duty Cycle
PCI(_F,1:6) Period
45
55
45
55
45
55
%
7,11,14
7,11,14
TPeriod
30.0
30.0
30.0
ns
Rev 1.0,November 20, 2006
Page 11 of 19