CY28341
S 1
S 2
W a it fo r
1 .1 4 6 m s
S a m p le
In p u ts
F S (3 :0 )
E n a b le
O u tp u te s
D e la y 0 .2 5 m S
V D D A = 2 .0 V
S 0
S 3
N o rm a l
O p e ra tio n
P o w e r O ff
V D D 3 .3 = O ff
Figure 7. Clock Generator Power-up/ Run State Diagram (with P4 Processor SELP4_K7# = 1)
Connection Circuit DDRT/C Signals
For Open Drain CPU Output Signals (with K7 Processor SELP4_K7# = 0)
3.3V
VDDCPU(1.5V)
Measurement Point
60.4 Ohm
500 Ohm
47 Ohm
ꢂꢃꢀOhmꢀꢀ5"
ꢂꢃꢀOhmꢀꢀ5"
ꢂꢃꢀOhmꢀꢀꢄ"
500 Ohm
CPUOD_T
680 pF
20 pF
301 Ohm
VDDCPU(1.5V)
ꢂꢃꢀOhmꢀꢀ1"
47 Ohm
500 Ohm
CPUOD_C
Measurement Point
680 pF
60.4 Ohm
20 pF
500 Ohm
3.3V
Figure 8.
6”
6”
Figure 9.
Rev 1.0,November 20, 2006
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