CY28341-3
Pin Description[2] (continued)
Pin Number
Pin Name
IREF
PWR
I/O
Pin Description
25
Current reference programming input for CPU buffers. A precise resistor
is attached to this pin, which is connected to the internal current reference.
I
28
SDATA
Serial Data Input. Conforms to the Phillips I2C specification of a Slave
I/O Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
27
26
SCLK
I
Serial Clock Input. Conforms to the Philips I2C specification.
PD#/SRESET#
Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0(default),
thispin becomes a SRESET# opendrainoutput. Seesystem resetdescription.
If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When
PD# is asserted low, the device enters power down mode. See power
management function.
I/O
PU
45
46
BUF_IN
FBOUT
Input to DDR Differential Buffers.
2.5V single-ended SDRAM buffered output of the signal applied at
BUF_IN.
5
VDDAGP
VDDC
3.3V power supply for AGP clocks.
3.3V power supply for CPUT/C clocks.
3.3V power supply for PCI clocks.
3.3V power supply for REF clock.
2.5V power supply for CPUCS_T/C clocks.
3.3V power supply for 48M.
3.3V Common power supply.
2.5V power supply for DDR clocks.
Ground for AGP clocks.
51
16
55
50
22
23
34,40
9
VDDPCI
VDDR
VDDI
VDD_48M
VDD
VDDD
VSSAGP
VSSPCI
VSSC
13
54
33,39
19
47
2
Ground for PCI clocks.
Ground for CPUT/C clocks.
Ground for DDR clocks.
VSSD
VSS_48M
VSSI
Ground for 48M clock.
Ground for CPUCS_T/C clocks.
Ground for REF.
VSSR
24
VSS
Common Ground.
Power Management Functions
Data Protocol
All clocks can be individually enabled or stopped via the
two-wire control interface. All clocks are stopped in the low
state. All clocks maintain a valid high period on transitions from
running to stop and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs
will stabilize to the correct pulse widths within about 0.5 mS.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Rev 1.0,November 21, 2006
Page 3 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
