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CY28341OC-3T 参数 Datasheet PDF下载

CY28341OC-3T图片预览
型号: CY28341OC-3T
PDF下载: 下载PDF文件 查看货源
内容描述: 通用时钟芯片为VIA ™ P4M / KT / KM400A DDR系统 [Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28341OC-3T的Datasheet PDF文件第2页浏览型号CY28341OC-3T的Datasheet PDF文件第3页浏览型号CY28341OC-3T的Datasheet PDF文件第4页浏览型号CY28341OC-3T的Datasheet PDF文件第5页浏览型号CY28341OC-3T的Datasheet PDF文件第6页浏览型号CY28341OC-3T的Datasheet PDF文件第7页浏览型号CY28341OC-3T的Datasheet PDF文件第8页浏览型号CY28341OC-3T的Datasheet PDF文件第9页  
CY28341-3  
Universal Clock Chip for VIA™P4M/KT/KM400A DDR Systems  
Features  
Table 1. Frequency Selection Table  
FS(3:0)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
CPU  
100.9  
100.0  
133.9  
133.3  
110.0  
145.2  
180.0  
198.4  
200.9  
200.0  
166.9  
166.6  
100.0  
133.3  
200.0  
166.6  
AGP  
67.3  
66.7  
66.9  
66.7  
73.3  
72.6  
72.0  
71.7  
66.9  
66.7  
66.8  
66.6  
66.7  
66.7  
66.7  
66.6  
PCI  
33.6  
33.3  
33.5  
33.3  
36.7  
36.3  
36.0  
35.8  
33.5  
33.3  
33.4  
33.3  
33.3  
33.3  
33.3  
33.3  
• Supports VIA P4M/KM/KT/266/333/400A chipsets  
• Supports Intel£ Pentium£ 4, Athlon™ processors  
• Supports two DDR DIMMS  
• Provides:  
— Two different programmable CPU clock pairs  
— Six differential DDR pairs  
— Three low-skew/-jitter AGP clocks  
— Seven low-skew/-jitter PCI clocks  
— One 48M output for USB  
— One programmable 24M or 48M for SIO  
• Dial-A-Frequency£ and Dial-A-dB¥ features  
• Spread Spectrum for best EMI reduction  
• Watchdog feature for system recovery  
• SMBus-compatible for programmability  
• 56-pin SSOP and TSSOP packages  
Pin Configuration[1]  
Block Diagram  
VDDR  
XIN  
REF(0:1)  
VDDI  
XTAL  
FS2  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
*FS0/REF0  
VSSR  
VTTPWRGD#/REF1  
VDDR  
VSSC  
CPUT/CPUOD_T  
CPUC/CPUOD_C  
VDDC  
XOUT  
REF0  
XIN  
XOUT  
VDDAGP  
AGP0  
*SELP4_K7/AGP1  
AGP2  
VSSAGP  
**FS1/PCI_F  
PCI1  
*MULTSEL/PCI2  
VSSPCI  
PCI3  
CPUCS_T/C  
FS0  
VDDC  
SELP4_K7#  
CPU(0:1)/CPU0D_T/C  
PLL1  
VDDI  
CPUCS_C  
CPUCS_T  
VSSI  
VDDPCI  
9
PCI(3:6)  
FS3 FS1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
FBOUT  
PCI_F  
MULTSEL  
PCI2  
BUF_IN  
DDRT0  
DDRC0  
DDRT1  
DDRC1  
VDDD  
PD#  
PCI1  
PCI4  
VDDPCI  
PCI5  
VDDAGP  
AGP(0:2)  
PCI6  
VSSD  
VDD48M  
48M  
VSS48M  
**FS3/48M  
**FS2/24_48M  
VDD48M  
VDD  
DDRT2  
DDRC2  
DDRT3  
DDRC3  
VDDD  
SDATA  
SCLK  
SMBus  
PLL2  
/ 2  
WDEN  
24_48M  
VSS  
VSSD  
IREF  
*PD#/SRESET#  
SCLK  
DDRT4  
DDRC4  
DDRT5  
DDRC5  
SRESET#  
VDDD  
WD  
SDATA  
FBOUT  
S2D  
Buf_IN  
56 pin SSOP  
DDRT(0:5)  
DDRC(0:5)  
CONVERT  
Note:  
1. Pins marked with [*] have internal 250 K:ꢀpull-up resistors. Pins marked with [**] have internal 250 K:ꢀpull-down resistors.  
Rev 1.0, November 21, 2006  
Page 1 of 19  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
www.SpectraLinear.com