CY28341-3
AC Parameters (continued)
100 MHz
133MHz
200 MHz
Min. Max. Unit
Parameter
24 MHz
Description
Min.
Max.
Min.
Max
Notes
TDC
24-MHz Duty Cycle
45
55
45
55
45
55
% 6,7,9
TPERIOD
TR / TF
TCCJ
24-MHz Period
41.660 41.667 41.660 41.667 41.660 41.667 ns 6,7,9
24-MHz Rise and Fall Times
24-MHz Cycle-to-Cycle Jitter
1.0
–
4.0
1.0
–
4.0
1.0
–
4.0
ns 7,8
500
500
500
ps 7,9,10
REF
TDC
REF Duty Cycle
45
69.8413
1.0
55
71.0
4.0
45
55
45
55
% 6,7,9
TPERIOD
TR / TF
TCCJ
REF Period
69.8413 71.0 69.8413 71.0
ns 6,7,9
ns 7,8
REF Rise and Fall Times
REF Cycle-to-Cycle Jitter
1.0
–
4.0
1.0
–
4.0
–
1000
1000
1000
ps 7,9,10
DDR
VX
Crossing Point Voltage of DDRT/C 0.5*VDD 0.5*VDDD 0.5*VDD 0.5*VDD 0.5*VDD 0.5*VDD
V
V
18
19
20
D–0.2
+0.2
D–0.2
D+0.2
D–0.2
D+0.2
VD
Differential Voltage Swing
0.7
VDDD
0.6
+
0.7
VDDD
0.6
+
0.7
VDDD
0.6
+
TDC
DDRT/C(0:5) Duty Cycle
DDRT/C(0:5) Period
45
9.997
1
55
45
55
45
55
%
TPERIOD
TR/TF
TSKEW
10.003 7.4978 7.5023 4.9985 5.0015 ns 20
DDRT/C(0:5) Rise/Fall Slew Rate
3
1
–
3
1
–
3
V/ns 8
DDRT/C to any DDRT/C Clock
Skew
–
100
100
100
ps 7,10,20
TCCJ
DDRT/C(0:5) Cycle-to-Cycle Jitter
DDRT/C(0:5) Half-period Jitter
BUF_IN to Any DDRT/C Delay
FBOUT to Any DDRT/C Skew
All-Clock Stabilization from Power-up
–
–
1
–
–
150
100
4
–
–
1
–
–
150
100
4
–
–
1
–
–
150
100
4
ps 7,10,20
ps 7,10,20
ns 7,9
THPJ
TDELAY
TSKEW
TSTABLE
100
3
100
3
100
3
ps 7,9
ms 13
Notes:
5. All outputs loaded as per maximum capacitive load table.
6. This parameter is measured as an average over a 1-us duration, with a crystal center frequency of 14.31818 MHz.
7. All outputs loaded as per loading specified in Table 11.
8. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V signals and between 20% and 80% for differential signals.
9. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V and 50% point for differential signals.
10. This measurement is applicable with Spread ON or spread OFF.
11. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals).
12. Probes are placed on the pins, and measurements are acquired at 0.4V.
13. The time specified is measured from when all VDDs reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the
specifications.
14. When Xin is driven from and external clock source (3.3V parameters apply).
15. When crystal meets minimum 40-ohm device series resistance specification.
.
16. Measured between 0.2V and 0.7V
DD
DD
17. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
18. The typical value of VX is expected to be 0.5*V (or 0.5*V
for CPUCS signals) and will track the variations in the DC level of the same.
DDC
DDD
19. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
20. Measured at VX, or where subtraction of CLK-CLK# crosses 0V.
21. Measured at VX between the rising edge and the following falling edge of the signal.
22. Measured from Vol = 0.175V to Voh = 0.525V.
23. See Figure 11 for 0.7V loading specification.
24. Measurement taken from differential waveform, from –0.35V to +0.35V.
25. Measurements taken from common mode waveforms, measure rise/fall time from 0.41V to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed for
waveform symmetry.
26. Measured in absolute voltage, i.e., single-ended measurement.
27. Probes are placed on the pins, and measurements are acquired between 0.8V and 2.0V signals and between 20% and 80% for differential signals.
Rev 1.0,November 21, 2006
Page 17 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
