CY28341-3
PD#
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
Figure 4. Power-down Assertion Timing Waveform (In K7 Mode)
Power-down Deassertion (K7 Mode)
When deasserted PD# to high level, all clocks are enabled and
start running on the rising edge of the next full period in order
to guarantee a glitch free operation, no partial clock pulses.
<1.5 m sec
PD#
CPUT 133MHz
CPUC 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)
Rev 1.0,November 21, 2006
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